The present invention generally relates to fabrication of semiconductor devices, and more particularly to the method for fabricating a semiconductor device including the step for forming an amorphous silicon layer followed by a crystallization step thereof.
In the fabrication of semiconductor devices, it is known to deposit a semiconductor layer in the amorphous state and to form a polycrystalline semiconductor layer from such an amorphous semiconductor layer. For example, a dynamic random access memory (DRAM) is formed by depositing a thin amorphous silicon layer first, followed by the formation of thin, fin-shaped electrodes of polysilicon. It should be noted that a stacked fin capacitor includes a number of electrode fins stacked upon each other. In the fabrication of such a stacked fin capacitor electrode, one or more amorphous silicon layers are deposited one after another, with intervening silicon oxide layers. As such a fabrication step includes the step of heating the amorphous silicon layer to a temperature of 800-1000.degree. C., the amorphous silicon layer generally experiences crystallization as a result of the high temperature. In other words, the amorphous silicon layer is converted to a polysilicon layer as a result of the heating. By forming the electrode of the stacked fin capacitor by way of deposition of an amorphous silicon layer, it becomes possible to obtain an electrode having an extremely smooth surface. Thus, by using the electrode having such a smooth surface, it becomes possible to deposit a very thin dielectric layer on the surface of the electrode without introducing therein defects such as a pinhole.
FIG.1 shows the structure of a conventional DRAM including a stacked fin capacitor.
Referring to FIG.1, the illustrated device is constructed on a p-type substrate 1 covered by a field oxide film 2, wherein the field oxide film 2 includes an aperture defining a device region 2a. Thus, the surface of the substrate 1 is exposed in correspondence to the device region 2a, and a polysilicon pattern forming a word line WL extends over the surface of the substrate thus exposed.
In the device region 2a, n.sup.+ -type diffusion regions 4 and 7 are formed at both sides of the word line WL acting as the gate of a MOS transistor Tr, as source and drain regions. Further, a p-type channel region CH is formed immediately below the word line. Although not illustrated, it should be noted that there is formed a thin gate insulation film underneath the word line WL acting as the gate, similarly to other MOS transistors. Further, another word line WL extends on the field oxide film 2 in parallel to the word line WL described previously.
On the field oxide film 2, an insulator layer 3 of silicon oxide is deposited such that the insulator layer 3 covers the word line WL as well as the device region 2a. Further, the insulator layer 3 is formed with contact holes 5 and 8 such that the contact holes expose the diffusion regions 4 and 7. On the insulator layer 3, a polysilicon pattern is provided as a bit line BL such that the bit line BL passes over the contact hole 8, wherein the bit line BL establishes a contact to the diffusion region 7 at the contact hole 8. On the other hand, a stacked fin capacitor Q is formed on the insulator layer 3 in correspondence to the contact hole 5 such that the capacitor Q is connected to the diffusion region 4 via the contact hole 5.
It should be noted that the stacked fin capacitor Q includes a hollow polysilicon trunk 6a contacted to the diffusion region 4 at the contact hole 5 and a fin region 6 formed of a number of thin polysilicon fins 6b-6d connected commonly to the trunk 6a, wherein the polysilicon fins 6b-6d extend laterally. Further, a thin dielectric film 6e of silicon oxide or silicon nitride (Si.sub.3 N.sub.4) is formed on the surface of the foregoing polysilicon fins 6b-6d as well as on the inner surface of the hollow trunk 6a. Further, there is provided a polysilicon layer forming an opposing electrode 6f at the outside of the dielectric film 6e such that the dielectric film 6e is sandwiched between the fin electrode 6 and the opposing electrode 6f. Generally, the electric charges accumulated in a capacitor increase with decreasing thickness of the dielectric film of the capacitor. Thus, it is desirable to reduce the thickness of the dielectric film 6e as much as possible in the stacked fin capacitor Q. In fact, a silicon nitride film having a thickness of about 7 nm is used for the dielectric film 6e.
When using such a thin dielectric film for the stacked fin capacitor, it is necessary to form the surface of the polysilicon fin as smooth as possible to avoid formation of defects such as a pinhole. Thus, it has been practiced to form the polysilicon fin by first depositing an amorphous silicon film by a vapor phase deposition process such as CVD (chemical vapor deposition), followed by a step of providing a conductivity thereto by way of ion implantation or other suitable doping process. As the amorphous silicon layer has an extremely smooth surface, the polysilicon layer formed as a result of crystallization of such an amorphous silicon layer also has a smooth surface.
On the other hand, the fabrication of semiconductor devices having a complex structure as in the case of the device of FIG. 1, includes a large number of fabrication steps, and there is a tendency that the throughput of production is reduced. In order to improve the throughput as much as possible, recent semiconductor plants use so-called cluster type production systems wherein unnecessary transport or storage process is minimized or eliminated. In the cluster type production system, various processing stations such as vapor phase deposition apparatuses and etching apparatuses are connected with each other by a transportation chamber. The product in fabrication is transported between various processing stations one by one via the transportation chamber, without contacting the air outside.
FIG. 2A shows an example of such a cluster type vapor phase deposition apparatus.
Referring to FIG. 2A, the apparatus includes a first reaction chamber 11a and a second reaction chamber 11b, as well as a transportation chamber 12 connecting the foregoing first and second reaction chambers 11a and 11b. Further, each of the reaction chambers has a construction shown in FIG. 2B.
Referring to FIG. 2B, the reaction chamber includes a shower nozzle 11.sub.1 supplied with a source gas via a piping 11.sub.2, and a substrate 11.sub.4 is held on a holder 11.sub.3 that includes therein a heater mechanism (not shown) such that the substrate 11.sub.4 faces the shower nozzle 11.sub.1. The source gas is introduced from the shower nozzle 11.sub.1 to the surface of the substrate 11.sub.4 heated by the heater mechanism, wherein the constituent atoms of the semiconductor layer to be deposited are released as a result of the pyrolytic decomposition of the source gas in the vicinity of the substrate 11.sub.4. In the vapor phase deposition apparatus of FIG. 2A, one may conduct the deposition of the amorphous silicon layer forming the fins 6b-6d in the first reaction chamber 11a and conduct the deposition of a dielectric film 6e on the foregoing amorphous silicon layer.
The substrate processed in the reaction chamber 11a is transported one by one to the reaction chamber 11b via the transport chamber 12, while the loading and unloading of the substrate to and from the transportation chamber 12 is carried out via a load gate 13. The transportation chamber 12 is filled with an inert gas such that the substrate does not contact with the air in the external environment even when it is transported between processing stations. By using such a cluster type vapor phase deposition apparatus, it becomes possible to eliminate the conventional processes, employed in the conventional stand alone type apparatuses, for storing half products obtained after the processing in the reaction chamber 11a and for transporting such half products for a long distance as a batch. As a result, the throughput of the production of semiconductor devices increases substantially.
FIG. 3 shows another example of the cluster type vapor phase deposition apparatus.
Referring to FIG. 3, the apparatus includes a first reaction chamber 11a' and a second reaction chamber 11b' connected with each other by a transportation chamber 12' and processes a plurality of substrates simultaneously in each of the reaction chambers. In correspondence to each of the reaction chambers 11a' and 11b', there is provided an external heating device such as an infrared lamp for heating the substrates in the reaction chamber. Thus, the apparatus of FIG. 3, capable of processing a plurality of substrates simultaneously, can realize a high throughput of production.
Meanwhile, the inventors of the present invention have discovered that the surface of the electrode fins 6b-6d becomes rough when a DRAM shown in FIG. 1 is fabricated by using such a cluster type vapor phase deposition apparatus, particularly in the step of crystallizing the amorphous silicon layer deposited in the reaction chamber 11a as the electrode fins 6b-6d. When the surface of the fins 6b-6d becomes rough, the chance that defects such as pinholes are formed in the thin dielectric film 6e on the amorphous silicon layer, increases substantially. When such a pinhole is formed, the capacitance of the capacitor decreases substantially. It is believed that such a rough surface develops as a result of the grain growth of silicon crystals at the time of crystallization of the amorphous silicon layer.
It should be noted that such a roughening of the surface of the silicon layer associated with the crystallization of the amorphous silicon layer appears characteristically when a cluster type production facility is used for increasing the throughput of production. As long as a conventional stand alone type apparatus is used, the problem does not emerge. Thus, there has been a problem in the conventional fabrication process of semiconductor devices, an example being a DRAM, in that the cluster type apparatus cannot be used effectively for improving the throughput of production.